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12-bit 400 msps a/d converter ad12400 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features 400 msps sample rate snr of 63 dbfs @128 mhz sfdr of 70 dbfs @128 mhz vswr of 1:1.5 wideband ac-coupled input signal conditioning enhanced spurious-free dynamic range single-ended or differential encode signal lvds output levels twos complement output data applications communications test equipment radar and satellite subsystems phased array antennasdigital beam forming multichannel, multimode receivers secure communications wireless and wired broadband communications wideband carrier frequency systems general description the ad12400 is a 12-bit analog-to-digital converter with a transformer-coupled analog input and digital post processing for enhanced sfdr. the product operates at a 400 msps conversion rate with outstanding dynamic performance in wideband carrier systems. the ad12400 requires 3.8 v analog, 3.3 v digital, and 1.5 v digital supplies and provides a flexible encode signal that can be differential or single-ended. no external reference is required. the ad12400 package style is an enclosed 2.9" 2.6" 0.6" module. performance is rated over a 0c to 60c case temperature range. functional block diagram 03735-0-001 adc a data ready a data ready b da0?da11 db0?db11 clk distribution ad12400 post- processing adc b a in clock distribution divide by 2 enc enc figure 1. product highlights 1. guaranteed sample rate of 400 msps. 2. input signal conditioning with optimized dynamic performance to 180 mhz. 3. additional performance options availablecontact factory. 4. proprietary advanced filter bank? digital post processing from vcorp? technologies, inc.
ad12400 rev. 0 | page 2 of 28 table of contents specifications..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications.......................................................................... 4 explanation of test levels ............................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 8 definitions of specifications ......................................................... 11 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 15 time-interleaving adcs ........................................................... 15 analog input ............................................................................... 16 clock input.................................................................................. 16 digital outputs ........................................................................... 16 power supplies ............................................................................ 16 start-up and reset ........................................................... 17 lead/lag ...................................................................................... 17 thermal considerations............................................................ 17 package integrity/mounting guidelines ................................. 18 ad12400 evaluation kit.......................................................... 19 power connector ................................................................... 19 analog input ........................................................................... 19 encode ..................................................................................... 19 data outputs........................................................................... 19 adapter card .......................................................................... 19 digital post processing control ........................................... 19 reset ...................................................................................... 19 layout guidelines........................................................................... 25 pcb interface .............................................................................. 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history revision 0: initial version
ad12400 rev. 0 | page 3 of 28 specifications dc specifications table 1. va = 3.8 v, vc = 3.3 v, vd = 1.5 v, encode = 400 msps, 0c t case 60c, unless otherwise noted. ad12400jws ad12400kws parameter case temp test level min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full iv guaranteed guaranteed offset error full i ?12 +12 ?12 +12 lsb gain error @ 10 mhz full i ?10 +10 ?10 +10 %fs differential nonlinearity (dnl) 60c v 0.3 0.3 lsb integral nonlinearity (inl) 60c v 0.5 0.5 lsb temperature drift gain error 60c v 0.02 0.02 %/c analog input (ain) full-scale input voltage range 60c v 3.2 3.2 v p-p frequency range full iv 10 180 10 180 mhz flatness (10 mhz-180 mhz) full iv 0.5 1 0.5 1 db input vswr (50 ? ) (10 mhzC180 mhz) 60c v 1.5 1.5 analog input bandwidth 60c v 450 450 mhz power supply 1 supply voltage va full iv 3.6 3.8 3.6 3.8 v vc full iv 3.2 3.4 3.2 3.4 v vd full iv 1.475 1.575 1.475 1.575 v supply current i va (va = 3.8 v) full i 0.95 1.11 0.95 1.11 a i vc (vc = 3.3 v) full i 400 500 400 500 ma i vd (vd = 1.5 v) full i 1.4 1.8 1.4 1.8 a total power dissipation full i 7.0 8.5 7.0 8.5 w encode inputs 2 differential inputs (enc, enc ) input voltage range full iv 0.4 0.4 v input resistance 60c v 100 100 ? input capacitance 60c v 4 4 pf common-mode voltage 60c v 3 3 v single-ended inputs (enc) input voltage full iv 0.4 2 2.5 0.4 2 2.5 v p-p input resistance 60c v 50 50 ? logic inputs ( reset ) 3 logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v source i ih 60c v 10 10 a source i il 60c v 1 1 ma logic outputs (dra, drb, output bits) 4 differential output voltage full iv 247 454 247 454 mv
ad12400 rev. 0 | page 4 of 28 ad12400jws ad12400kws logic outputs output drive current full iv ?4 +4 ?4 +4 ma output common-mode voltage full iv 1.125 1.375 1.125 1.375 v start-up time full iv 600 600 ms 1 tested using input frequency of 70 mhz. see figure 17 for i(vd ) variation vs. input frequency. 2 all ac specifications tested by driving enc single-ended. 3 refer to table 5 for logic convention on all logic inputs. 4 digital output logic levels: dr v = 3.3 v, c load = 8 pf. 3.3 v lvds r1 = 100 ?. specifications subject to change without notice. ac specifications 1 table 2. va = 3.8 v, vc = 3.3 v, vd = 1.5 v, encode = 400 msps, 0c t case 60c, unless otherwise noted. ad12400jws ad12400kws parameter case temp test level min typ max min typ max unit dynamic performance 2 snr analog input 10 mhz full i 62 64.4 62 64.4 dbfs @ ?1.0 dbfs 70 mhz full i 61.5 64 61.5 64 dbfs 128 mhz full i 60 63.5 60 63.5 dbfs 180 mhz full i 60 62.5 60 62.5 dbfs sinad 3 analog input 10 mhz full i 61 64 61 64 dbfs @ ?1.0 dbfs 70 mhz full i 60.5 64 60.5 64 dbfs 128 mhz full i 59 62.5 59 62.5 dbfs 180 mhz full i 57 61 57 61 dbfs spurious-free dynamic range 3 analog input 10 mhz full i 69 80 69 80 dbfs @ ?1.0 dbfs 70 mhz full i 69 84 69 84 dbfs 128 mhz full i 67 76 67 76 dbfs 180 mhz full i 62 71 62 71 dbfs image spur 4 analog input 10 mhz full i 60 75 62 75 dbfs @ ?1.0 dbfs 70 mhz full i 60 72 62 72 dbfs 128 mhz full i 56 70 62 70 dbfs 180 mhz full i 54 70 62 70 dbfs offset spur 4 60c v 65 65 dbfs analog input @ ?1.0 dbfs two-tone imd 5 f1, f2 @ ?6 dbfs 60c v ?75 ?75 dbc switching specifications conversion rate 6 full iv 396 400 404 396 400 404 msps encode pulsewidth high (t eh ) 1 60c v 1.25 1.25 ns encode pulsewidth low (t el ) 1 60c v 1.25 1.25 ns digital output parameters valid time (t v ) full iv 1.9 2.4 3.1 1.9 2.4 3.1 ns propagation delay (t pd ) 60c v 1.20 1.20 ns rise time (t r ) (20% to 80%) 60c v 1 1 ns fall time (t f ) (20% to 80%) 60c v 1 1 ns
ad12400 rev. 0 | page 5 of 28 ad12400jws ad12400kws parameter case temp test level min typ max min typ max unit dr propagation delay (t edr ) 60c v 3.88 3.88 ns data to dr skew (t edr ? t pd ) 60c v 2.68 2.68 ns pipeline latency 7 full iv 40 40 cycles aperture delay (t a ) 60c v 1.6 1.6 ns aperture uncertainty (jitter, t j ) 60c v 0.4 0.4 ps rms 1 all ac specifications tested wi th a single-ended 2.0 v p-p encode. 2 dynamic performance guaranteed for analog input frequencies of 10 mhz to 180 mhz. 3 not including image spur. 4 image spur will be at fs/2 ? a in and the offset spur will be at fs/2. 5 f1 = 70 mhz, f2 = 73 mhz. 6 parts are tested with 400 msps en code. device can be clocked at lower encode rates, but specif ications are not guaranteed. spe cifications will be guaranteed by design for encode 400 msps 1%. 7 pipeline latency will be exactly 40 cycles. explanation of test levels i 100% production tested. ii 100% production tested at 25c and samp le tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and ch aracterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ad12400 rev. 0 | page 6 of 28 absolute maximum ratings table 3. parameter value va to agnd 5 v vc to dgnd 4 v vd to dgnd 1.65 v analog input voltage 6 v (dc) analog input power 18 dbm (ac) encode input voltage 6 v (dc) encode input power 12 dbm (ac) logic inputs and outputs to dgnd 5 v storage temperature range, ambient ?65c to +150c operating temperature 0c to 60c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad12400 rev. 0 | page 7 of 28 table 4. output coding (twos complement) code ain (v) digital output 4095 +1.6 0111 1111 1111 . . . . . . . . . 2048 0 0000 0000 0000 2047 ?0.000781 1111 1111 1111 . . . . . . 0 ?1.6 1000 0000 0000 table 5. option pin list with necessary associated circuitry pin name active high or low logic level type default level associated circuitry within part reset low lvttl high 3.74 k? pull-up lead/lag low lvttl low 10 k? ? 60 k? pull-down 03735-0-003 encode 100 ? encode 100 ? 100 ? 100 ? 3.3v 3.3v pecl driver figure 2. encode equivalent circuit encode 400mhz dra drb drb dra data out b lead lag data out a *data lost due to assertion of lead/lag. latency of 40 encode clock cycles before data valid. n ? 40 n? 1 n ? 39 n n n + 2 n + 1 n + 1 n + 2 n + 3 n + 3 n + 5 n + 7 n + 4 n + 6 n + 8 1/f s t el t eh * * 40 clock cycles notes: 1 if a single-ended sinewave is used for encode, use the "zero crossing" point (ac-coupled) as the 50% point and apply the same timing information. 2 the lead/lag pin is used to synchronize the collection of data into external buffer memories. the lead/lag pin can be applied synchronously or asynchronously to the ad12400. if applied asynchronously, lead/lag must be held high for a minimum of 5ns to ensure correct operation. the function will shut off dra and drb until the lead/lag pin is released. dra and drb will resume on the next valid dra after lead/lag is released. 03735-0-002 figure 3. timing diagram 03735-0-004 t pd t v enc data out dr enc dr figure 4. highlighted timing diagram
ad12400 rev. 0 | page 8 of 28 pin configuration and fu nction descriptions 03735-0-005 samtec connector qte-060-01-l-d-a-k-tr bottom view left side view ain enc board *integral ground plane connections. section a = dgnd, pins 121?124. section b = dgnd, pins 125?128. section c = agnd, pins 129?132. notes for mating half, use samtec, inc. part no. qse-60-01-l-d-a-k. enc 2-56 studs 4 johnson sma-50 ohm connect no. 142-0711-821 end view top view pin 1 ain enc enc db0+ db0? db2+ db2? db4+ db4? db6+ db6? db8+ db8? db10+ db10? dnc dnc drb drb dnc dnc vc vc db1+ db1? db3+ db3? db5+ db5? db7+ db7? db9+ db9? db11+ db11? dnc dnc dnc dnc dnc reset vc vc * dra dra da0+ da0? da2+ da2? da4+ da4? da6+ da6? da8+ da8? da10+ da10? dnc pass vd vd vd vd dnc lead/lag da1+ da1? da3+ da3? da5+ da5? da7+ da7? da9+ da9? da11+ da11? dnc dnc vd vd vd vd pin 120 pin 2 pin 40 a b c pin 1 pin 119 * va va va va agnd agnd dnc dnc dnc dnc dnc dnc dnc agnd agnd agnd agnd agnd agnd agnd va va va va agnd agnd dnc dnc dnc dnc dnc dnc agnd agnd agnd agnd agnd agnd agnd agnd * pin 80 pin 79 pin 39 figure 5. pin configuration
ad12400 rev. 0 | page 9 of 28 table 6. pin function descriptions pin number mnemonic function 1, 2, 3, 4 vc digital supply, +3.3 v. 5 reset lvttl. 0 = device reset. minimum width = 200 ns. device resumes operation after 600 ms maximum. 6?9, 11, 13?16, dnc do not connect. 49, 51?52, 79, 96?108 10 drb channel b data ready. complement output. 12 drb channel b data ready. true output. 17 db11? channel b data bit 11. complement output bit. 18 db10? channel b data bit 10. complement output bit. 19 db11+ channel b data bit 11. true output bit. 20 db10+ channel b data bit 10. true output bit. 21 db9? channel b data bit 9. complement output bit. 22 db8? channel b data bit 8. complement output bit. 23 db9+ channel b data bit 9. true output bit. 24 db8+ channel b data bit 8. true output bit. 25 db7? channel b data bit 7. complement output bit. 26 db6? channel b data bit 6. complement output bit. 27 db7+ channel b data bit 7. true output bit. 28 db6+ channel b data bit 6. true output bit. 29 db5? channel b data bit 5. complement output bit. 30 db4? channel b data bit 4. complement output bit. 31 db5+ channel b data bit 5. true output bit. 32 db4+ channel b data bit 4. true output bit. 33 db3? channel b data bit 3. complement output bit. 34 db2? channel b data bit 2. complement output bit. 35 db3+ channel b data bit 3. true output bit. 36 db2+ channel b data bit 2. true output bit. 37 db1? channel b data bit 1. complement output bit. 38 db0? channel b data bit 0. co mplement output bit. db0 is lsb. 39 db1+ channel b data bit 1. true output bit. 40 db0+ channel b data bit 0. true output bit. db0 is lsb. 41?48 vd digital supply, +1.5 v. 50 pass lvttl. factory use only. (dnc) 53 da11? channel a data bit 11. complement output bit. 54 da10? channel a data bit 10. complement output bit. 55 da11+ channel a data bit 11. true output bit. 56 da10+ channel a data bit 10. true output bit. 57 da9? channel a data bit 9. complement output bit. 58 da8? channel a data bit 8. complement output bit. 59 da9+ channel a data bit 9. true output bit. 60 da8+ channel a data bit 8. true output bit. 61 da7? channel a data bit 7. complement output bit. 62 da6? channel a data bit 6. complement output bit. 63 da7+ channel a data bit 7. true output bit. 64 da6+ channel a data bit 6. true output bit. 65 da5? channel a data bit 5. complement output bit. 66 da4? channel a data bit 4. complement output bit. 67 da5+ channel a data bit 5. true output bit.
ad12400 rev. 0 | page 10 of 28 pin number mnemonic function 68 da4+ channel a data bit 4. true output bit. 69 da3? channel a data bit 3. complement output bit. 70 da2? channel a data bit 2. complement output bit. 71 da3+ channel a data bit 3. true output bit. 72 da2+ channel a data bit 2. true output bit. 73 da1? channel a data bit 1. complement output bit. 74 da0? channel a data bit 0. co mplement output bit. da0 is lsb. 75 da1+ channel a data bit 1. true output bit. 76 da0+ channel a data bit 0. true output bit. da0 is lsb. 77 lead/lag typically dnc. see lead/lag note on page 17. 78 dra channel a data ready. complement output. 80 dra channel a data ready. true output. 81?95, 109?112, 129?132* agnd analog ground. 113?120 va analog supply, 3.8 v 121?128* dgnd digital ground. *internal ground plane connectio ns: section a = dgnd, pi ns 121?124, section b = dg nd, pins 125?128, section c = agnd, pins 129? 132.
ad12400 rev. 0 | page 11 of 28 definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point on the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. full-scale input voltage range this is the maximum peak-to-peak input signal magnitude that will result in a full-scale response, 0 dbfs on a single-tone input signal case. any magnitude increase from this value will result in an over-range condition. analog input vswr (50 ?) the voltage standing wave ratio is a ratio of the transmitted and reflected signals. the vswr can be related to input impedance using the following equations: impedance reference impedance load actual 1 1 = = + ? = + ? = s z l z vswr s z l z s z l z differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) calculated from the measured snr based on the equation 02 . 6 76 . 1 db snr enob measured ? = encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time the encode pulse should be left in logic 1 state to achieve rated perform- ance; pulsewidth low is the minimum time the encode pulse should be left in low state. see timing implications of changing t ench in the application notes, encode input section. at a specified clock rate of 400 msps, these specifications define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: () ? ? ? ? ? ? ? ? = ? ? 001 . 0 log 10 2 input scalerms full scale full z v power gain error the difference between the measured and ideal full-scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbfs. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbfs. distortion, image spur the ratio of the rms signal amplitude to the rms signal amplitude of the image spur, reported in dbfs. the image spur, a result of gain and phase errors between two time-interleaved conversion channels, is located at fs/2 C f ain . distortion, offset spur the ratio of the rms signal amplitude to the rms signal amplitude of the offset spur, reported in dbfs. the offset spur, a result of offset errors between two time-interleaved conversion channels, is located at fs/2. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the minimum encode rate at which the image spur calibration will degrade no more than 1 db (when image spur is 70 db). maximum conversion rate the maximum encode rate at which the image spur calibration will degrade no more than 1 db (when image spur is 70 db). output propagation delay the delay between a differential crossing of encode and encode (or zero crossing of a single-ended encode). total noise calculated as follows: ? ? ? ? ? ? ? ? = 10 10 001 . 0 dbfs dbc dbm signal snr fs noise z v where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the value of the particular input level, and signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise.
ad12400 rev. 0 | page 12 of 28 offset error the dc offset imposed on the input signal by the adc, reported in lsb (codes). pipeline latency the number of clock cycles that the output data will lag the corresponding clock cycle. power supply rejection ratio the ratio of power supply voltage change to the resulting adc output voltage change. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc and image spur. signal-to-noise ratio (snr) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, except the image spur. the peak spurious component may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or dbfs (always related back to converter full-scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full-scale).
ad12400 rev. 0 | page 13 of 28 typical performance characteristics note x = image spur n = interleaved offset spur 03735-0-006 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 20 40 60 80 100 120 140 160 180 200 snr = 63.3db sfdr = 75dbc sinad = 62.9db image spur = 80.5dbc 2 3 4 5 6 x n frequency (mhz) db figure 6. fft: f s = 400 msps, a in = 10.123 mhz @ C1.0 dbfs ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 03735-0-007 0 20 40 60 80 100 120 140 160 180 200 snr = 63.1db sfdr = 78.7dbc sinad = 62.7db image spur = 78.8dbc 2 3 4 5 6 frequency (mhz) db n x figure 7. fft: f s = 400 msps, a in = 65.123 mhz @ C1.0 dbfs ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 03735-0-008 0 20 40 60 80 100 120 140 160 180 200 snr = 62.5db sfdr = 69.9dbc sinad = 61.1db image spur = 73.4dbc 2 3 4 5 6 x frequency (mhz) db n figure 8. fft: f s = 400 msps, a in = 128.123 mhz @ C1.0 dbfs ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 03735-0-009 0 20 40 60 80 100 120 140 160 180 200 snr = 61.6db sfdr = 69.0dbc sinad = 60.0db image spur = 70.4dbc 2 3 4 5 6 x n frequency (mhz) db figure 9. fft: f s = 400 msps, a in = 180.123 mhz @ C1.0 dbfs ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 03735-0-010 0 20 40 60 80 100 120 140 160 180 200 sfdr = 76.3dbc frequency (mhz) db x1 n f2 ? f1 2f1 ? f2 2f1 + f2 2f2 + f1 2f2 ? f1 f2 + f1 x2 figure 10. two-tone intermodulation distortion (25.1 mhz and 28.1 mhz; f s = 400 msps) 03735-0-011 0 20 40 60 80 100 120 140 160 180 200 sfdr = 77.3dbc frequency (mhz) db ? 1 2 0 ? 1 1 0 ? 1 0 0 ? 9 0 ? 8 0 ? 7 0 ? 6 0 ? 5 0 ? 4 0 ? 3 0 ? 2 0 ? 1 0 0 f2 ? f1 2f1 ? f2 2f1 + f2 2f2 + f1 2f2 ? f1 f2 + f1 x2 x1 n figure 11. two-tone intermodulation distortion (70.1 mhz and 73.1 mhz; f s = 400 msps)
ad12400 rev. 0 | page 14 of 28 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 03735-0-036 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) magnitude (db) f2 ? f1 sfdr = 70dbc f1 + f2 x2 x1 2f1 + f2 2f2 + f1 2f1 ? f2 2f2 ? f1 figure 12. two-tone intermodulation distortion (178.1 mhz and 182.1 mhz; fs = 400 msps) sfdr = 70 dbc 03735-0-012 frequency (mhz) gain (db) ?0.4 ?0.5 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 10.7 35.0 59.3 83.6 107.9 132.2 156.5 180.8 205.1 229.4 figure 13. interleaved gain flatness 03735-0-013 analog input level (db) distortion (dbfs) 60 95 90 85 80 75 70 65 100 060 50 40 30 20 10 70 third harmonic second harmonic image spur figure 14. 2nd/3rd harmonics and image spur vs. analog input level f s = 400 msps, a in = 70 mhz 03735-0-014 analog input frequency (mhz) harmonics (dbc) 60 65 70 75 80 85 90 95 0 20 40 60 80 100 120 140 160 180 second harmonic image spur third harmonic figure 15. harmonics vs. analog input frequency 03735-0-015 analog input frequency (mhz) snr (dbfs) 62.8 64.4 64.2 64.0 63.8 63.6 63.4 63.2 63.0 64.6 0 20 40 60 80 100 120 140 160 180 figure 16. snr vs. analog input frequency 03735-0-016 input frequency (mhz) vd supply current (a) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 0 20 40 60 80 100 120 140 160 180 200 figure 17. +vd current vs. a in frequency
ad12400 rev. 0 | page 15 of 28 theory of operation the ad12400 uses two high-speed, 12-bit analog-to-digital converters (adcs) in a time-interleaved configuration to double the sample rate, while maintaining a high level of dynamic range performance. the digital output of each adc channel is calibrated using a proprietary digital post processing technique, advanced filter bank (afb tm ), from vcorp technologies. afb is implemented using a state-of-the-art field programmable gate array (fpga) and provides a wide bandwidth, wide temperature match for any gain, phase, and clock timing errors between each adc channel. time-interleaving adcs when two adcs are time-interleaved, gain and/or phase mismatches between each channel will produce an image spur at fs/2 C f ain and an offset spur as shown in figure 18. these mismatches can be the result of any combination of device tolerance, temperature, and frequency deviations. . ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 03735-0-017 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) db image spur 1 2 3 4 5 6 n offset spur x figure 18. image spur due to mismatches between two interleaved adcs (no afb digital post processing) figure 19 displays the performance of a similar converter with on-board, afb post processing implemented. the C44 dbfs image spur has been reduced to C77 dbfs and as a result, the dynamic range of this time-interleaved adc is no longer limited by the channel matching. 03735-0-018 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) db ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 image spur offset spur 1 2 3 4 5 6 n x figure 19. ad12400 with afb digital post processing the relationship between image spur and channel mismatches is captured in table 7 for specific conditions. table 7. image spur vs. channel mismatch gain error (%) aperture delay error (ps) image spur (dbc) 1 15 C40 0.25 2.7 C54 0.2 1.1 C62 0.025 0.5 C70 for a more detailed description of time-interleaving in adcs and a design example using the ad12400, refer to advanced digital post-processing techniques enhance performance in time interleaved adc systems, published in the august, 2003 edition of analog dialogue. this article can be found at http://www.analog.com/analogdialogue.
ad12400 rev. 0 | page 16 of 28 analog input the ad12400 analog input is ac-coupled using a proprietary, transformer front end circuit that provides 1 db of gain flatness over the first nyquist zone and a C3 db bandwidth of 450 mhz. this front end circuit provides a vswr of 1.5 (50 ) over the first nyquist zone, and the typical full-scale input is 3.2 v p-p the minicircuits hela-10 amplifier module can be used to drive the input at these power levels. clock input the ad12400 requires a 400 msps encode that is divided by 2 and distributed to each adc channel, 180 out of phase from each other. internal ac-coupling and bias networks provide the framework for flexible clock input requirements that include single-ended sine-wave, single-ended pecl, and differential pecl. while the ad12400 is tested and calibrated using a single-ended sine-wave, properly designed pecl circuits that provide fast slew rates (>1v/ns) and minimize ringing will result in comparable dynamic range performance. there are two major factors to consider when designing the input clock circuit for the ad12400: aperture jitter and harmonic content. the relationship between aperture jitter and snr can be characterized using the following equation. the equation assumes a single-tone full-scale input signal. ( ) ) (lsb noise input adc (lsb) dnl adc (bits) resolution adc jitter aperture frequency input 2 2 2 2 2 2 1 5 . 1 1 2 0 2 log 20 rms noise v n jrms t a f n v n t f snr noiserms jrms a = = = = = + + + ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 20 displays the application of this relationship to full- scale, single-tone input signal on the ad12400, where the dnl was assumed to be 0.4 lsb, and the input noise was assumed to be 0.8 lsbrms. the vertical marker at 0.4 ps displays the snr at the jitter level present in the ad12400 evaluation system, including the jitter associated with the ad12400 itself. 57 58 59 60 61 62 63 64 65 03735-0-037 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 aperture jitter (ps rms) snr (db) a in = 10mhz a in = 65mhz a in = 128mhz a in = 180mhz figure 20. snr vs. aperture jitter in addition to jitter, the harmonic content of single-ended sine wave clock sources must be controlled as well. the clock source used in the test and calibration process has a harmonic performance that is better than 60 dbc. also, when using pecl or other square-wave clock sources, unstable behavior such as overshoot and ringing can affect phase matching and degrade the image spur performance digital outputs the ad12400s digital post processing circuit provides two parallel, 12-bit 200 msps data output buses. by providing two output busses that operate at one half the conversion rate, the ad12400 eliminates the need for large, expensive, high power demultiplexing circuits. the output data format is twos complement, maintaining the standard set by other high speed a/d converters such as the ad9430 and ad6645. data-ready signals are provided for facilitating proper timing in the data capture circuit. finally, the digital post processing circuit can be configured to provide alternate data output formats. contact the factory for more details. power supplies the ad12400 requires three different supply voltages: a 1.5 v supply for the digital post processing circuit, a 3.3 v supply to facilitate digital i/o through the system, and a 3.8 v supply for the analog conversion and clock distribution circuits. the ad12400 incorporates two key features that result in solid power supply rejection ratio (psrr) performance. first, on- board linear regulators are used to provide an extra level of power supply rejection for the analog circuits. the linear regulator used to supply the a/d converters provides an additional 60 db of rejection at 100 khz. second, in order to address higher frequency noise (where the linear regulators rejection degrades), the ad12400 incorporates high quality ceramic decoupling capacitors.
ad12400 rev. 0 | page 17 of 28 while this product has been designed to provide good psrr performance, systems designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed adc systems. switching power supplies typically produce both conducted and radiated energy that result in common-/differential-mode emi currents. any system that requires 12-bit performance has very little room for errors associated with power supply emi. for example, a system goal of 74 db dynamic range performance on the ad12400 will require noise currents that are less than 4.5 a and noise voltages of less than 225 v in the analog input path. start-up and reset the ad12400s fpga configuration is stored in the on-board eprom and loaded into the fpga when power is applied to the device. the reset pin (active low) allows the user to reload the fpga in case of a low digital supply voltage condition or a power supply glitch. pulling the reset pin low will pull the data ready and output bits high until the fpga has been reloaded. the reset pin should remain low for a minimum of 200 ns. on the rising edge of the reset pulse, the ad12400 will start loading the configuration into the fpga. the reload process requires a maximum of 600 ms to complete. valid signals on the data ready pins indicate that the reset process is complete. also, system designers need be aware of the thermal conditions of the ad12400 at start-up. if large thermal imbalances are present, the ad12400 may require additional time to stabilize before providing specified image spur performance. lead/lag the lead/lag pin is used to synchronize the collection of data into external buffer memories. the lead/lag pin can be applied synchronously or asynchronously to the ad12400. if applied asynchronously, lead/lag must be held high for a minimum of 5 ns to ensure correct operation. the function will shut off dra and drb until the lead/lag pin is released. dra and drb will resume on the next valid dra after lead/lag is released. if this feature is not required, tie this pin to dgnd. thermal considerations the module is rated to operate over a case temperature of 0c to 60c. in order to maintain the tight channel matching and reliability of the ad12400, care must be taken to assure that proper thermal and mechanical considerations have been made and addressed to assure case temperature is kept within this range. each application will require evaluation of the thermal management as applicable to the system design. the following provides information that should be used in the evaluation of ad12400 thermal management for each specific use. in addition to the radiation of heat into its environment, the ad12400 module enables flow of heat through the mounting studs and standoffs as they contact the motherboard. as described in the package integrity/mounting guidelines section, the module should be secured to the motherboard using 2-56 nuts (washer use is optional). the torque on the nuts should not exceed 32 inch ounces. use of a thermal grease at the standoffs will result in better thermal coupling between the board and module. depending on the ambient conditions, air flow may be necessary to ensure the components in the module do not exceed their maximum operating temperature. in terms of reliability, the most sensitive component has a maximum junction temperature rating of 125c. figures 21 and 22 provide a basic guideline for two key thermal management decisions: the use of thermal interface material between the module bottom cover/mother board and airflow. figure 21 characterizes the typical thermal profile of an ad12400 that is not using thermal interface material. figure 22 provides the same information for a configuration that uses gap-filling thermal interface material (in this case thermagon t-flex 600 series, 0.040 thickness was used). one can see from these profiles that the maximum die temperature is reduced by approximately 2c when thermal interface material is used. figures 21 and 22 also provide a guideline for determining the airflow requirements for given ambient conditions. for example, a goal of 120c die temperature in a 40c ambient environment without the use of thermal interface material would require an air flow of 100 lfm. see the ad12400 thermal management and measurement application note for further details. from a channel matching perspective, the most important consideration will be external thermal influences. it is possible for thermal imbalances in the end application to adversely affect the dynamic performance. due to the temperature dependence of the image spur, substantial deviation from the factory calibration conditions can have a detrimental effect. unbalanced thermal influences can cause gradients across the module, and performance degradation may result. examples of unbalanced thermal influences may include large heat dissipating elements near one side of the ad12400 or obstructed air flow that does not flow uniformly across the module. the thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2c.
ad12400 rev. 0 | page 18 of 28 03735-0-019 airflow condition temperature ( c) 20 30 40 50 60 70 80 90 100 110 120 130 typical junction case ambient no air flow 100 lfm 300 lfm figure 21. typical temperature vs. air flow with no module/board interface material (normalized to 60c module case temperature) 03735-0-020 airflow condition temperature ( c) 20 30 40 50 60 70 80 90 100 110 120 130 typical junction case ambient no air flow 100 lfm 300 lfm figure 22. typical temperature vs. air flow with t-flex module/board interface material (normalized to 60c module case temperature ambient) package integrity/mounting guidelines the ad12400 is a printed circuit board (pcb) based module designed to provide mechanical stability and support the intricate channel-to-channel matching necessary to achieve high dynamic range performance. the module should be secured to the motherboard using 2-56 nuts (washer use is optional). the torque on the nuts should not exceed 32 inch ounces. the sma edge connectors (ain, enc/enc) are surface mounted to the board in order to achieve minimum height of the module. when attaching and routing the cables, one must ensure they are stress-relieved and do not apply stress to the sma connector/board. the presence of stress on the cables may degrade electrical performance and mechanical integrity of the module. in addition to the routing precautions, the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the ad12400s sma connectors. in no case should the torque exceed 5 inch pounds. any disturbances to the ad12400 structure, including removing the covers or mounting screws, will invalidate the calibration and result in degraded performance. refer to the outline dimensions section for mounting stud dimensions. refer also to figure 37 for pcb interface locations. mounting stud length will typically accommodate a pcb thickness of 0.093". consult the factory if board thickness requirements exceed this dimension.
ad12400 rev. 0 | page 19 of 28 ad12400 evaluation kit the ad12400/kit offers an easy way to evaluate the ad12400. the ad12400/kit includes the ad12400kws mounted on an adapter card, the ad12400 evaluation board, the power supply cables, a 225 mhz buffer memory fifo board, and the dual analyzer software. the user must supply a clock source, an analog input source, a 1.5 v power supply, a 3.3 v power supply, a 5 v power supply, and a 3.8 v power supply. the clock source and analog input source connect directly to the ad12400kws. the power supply cables (included) and a parallel port cable (not included) connect to the evaluation board. power connector power is supplied to the board via a detachable 12-lead power strip (three 4 pin blocks). table 8. power connector va 3.8 v analog supply for the adc (950 ma typical) vc 3.3 v digital supply for the adc outputs (200 ma typical) vd 1.5 v* digital supply for the fpga (2.5 a max, 1.4 a typical) vb 5.0 v digital supply for the buffer memory board (400 ma typical) *the power supply cable has approximately 100 mv drop. the vd supply current is dependent upon the analog input frequency. refer to figure 17. analog input the analog input source connects directly to an sma on the ad12400kws. encode the single-ended or differential encode signal connects directly to sma connector(s) on the ad12400kws. a single-ended sine wave at 10 dbm connected to the encode sma is recom- mended. a low jitter clock source is recommended (<0.5 ps) to properly evaluate the ad12400. data outputs the ad12400kws digital outputs are available at the 80-pin connector, p2, on the evaluation board. the ad12400/kit comes with a buffer memory fifo board connected to p2 that provides the interface to the parallel port of a pc. the dual analyzer software is compatible with windows? 95, windows? 98, windows? 2000, and windows nt?. the buffer memory fifo board can be removed and an external logic analyzer, or other data acquisition module, can be connected to this connector if required. adapter card the ad12400kws is attached to an adapter card that interfaces to the evaluation board through a 120-pin connector, p1, which is on the top side of the evaluation board. digital post processing control the ad12400 has a two-pin jumper labeled afb that allows the user to enable/disable the digital post processing. the digital post processing is active when the afb jumper is applied. when the jumper is removed, the fpga is set to a pass through mode, which will demonstrate to the user the performance of the ad12400 without the digital post processing. reset the ad12400kwss fpga configuration is stored in an eeprom and loaded into the fpga when power is applied to the ad12400. the reset switch, sw1 (active low), allows the user to reload the fpga in case of a low voltage condition or a power supply glitch. depressing the reset switch will pull the data ready and output bits high. the reset switch should remain low for a minimum of 200 ns. on the rising edge of the reset pulse, the ad12400 will start loading the configuration into the on-module fpga. the reload process requires a maximum of 600 ms to complete. valid signals on the data- ready pins indicate that the reset process is complete. the ad12400 is not compatible with the hsc-adc-eval- dc/sc hardware or software.
ad12400 rev. 0 | page 20 of 28 table 9. evaluation board bill of materials item no. quantity ref-des device package value 1 2 c3, c5 capacitor 603 0.1 f 25 v 2 2 c4, c6 capacitor 805 10 f 6.3 v 3 1 r9 resistor 603 4.02 k? 1% 4 1 afb 2 pin header/jumper pin strip molex/gc/weldon 5 1 p2 80 pin dual connector asse mble surface mount post header amp 6 1 sw1 switch push button spst 6 mm panasonic 7 3 j2, j3, j4 4 pin header power connecter pin strip wieland 8 1 p1 60 pin dual-socket assembly surface mount samtec 9 1 pcb ad12400 interface bd gs08054 pcb 03735-0-021 afb 3.3vc pass h/l_gain 3.3vc h/l_gain nyq 3.3vc nyq dither jp2 e12 jp3 e13 spare1 e14 spare2 e18 3.3vc other spare1 spare2 dgnd 1.5vd digital j3 1 2 3 4 dgnd +va agnd analog j2 1 2 3 4 digital j4 3.3vc 3.8v dgnd 1 2 3 4 5v c4 10 f c3 0.1 f dgnd dgnd 5v 5v c6 10 f c5 0.1 f 3.3vc dgnd dgnd 3.3vd 3.3vd select d jp4 e17 select d reset 1.5v sense e22 dgnd evq-pac85r 1 2 3 4 e1 r8 4.02k ? r9 4.02k ? r10 4.02k ? r11 4.02k ?
ad12400 rev. 0 | page 21 of 28 03735-0-022 drb dnc 3.3vc dnc dnc 3.3vc dnc reset db10 dnc dnc dnc db8 db9 db10 db11 db4 db5 db6 db7 db2 db3 db0 db1 14 16 18 20 22 24 26 28 30 32 34 36 38 40 122 124 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 121 123 4 6 8 10 12 p1:a dgnd qse?60?01?l?d?a?k dgnd dnc drb dnc db8 db6 db4 db2 db0 gnd gnd gnd gnd db11 db9 db7 db5 db3 db1 db11 pass 1.5vd 1.5vd da10 da11 dnc da8 da7 da10 da9 da4 da3 da6 da5 da2 da1 da0 dra lead/lag 54 56 58 60 62 64 66 68 70 72 74 76 78 80 126 128 42 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 125 127 44 46 48 50 52 p1:b dgnd qse?60?01?l?d?a?k dgnd dnc da8 da6 da4 da2 da0 dra gnd gnd gnd gnd da11 da9 da7 da5 da3 da1 dnc dnc agnd agnd 3.3vc dnc dnc dnc wp 94 96 98 100 102 104 106 108 110 112 114 116 118 120 130 132 82 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 129 131 84 86 88 90 92 p1:c agnd agnd qse?60?01?l?d?a?k agnd agnd dnc gnd gnd gnd e2 e19 dnc dnc dnc dnc dnc +va +va 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 dgnd p2:c amp104655-9 dra da11 da10 dra da11 da10 da9 da9 da8 da8 da7 da7 da6 da6 da5 da5 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p2:d amp104655-9 da3 da1 da0 da3 da2 da2 da4 da4 da1 da0 or or 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dgnd p2:a amp104655-9 drb db11 db10 drb db11 db10 db9 db9 db8 db8 db7 db7 db6 db6 db5 db5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p2:b amp104655-9 db3 db1 db0 db3 db2 db2 db4 db4 db1 db0 or or ad12400 figure 24. evaluation board
ad12400 rev. 0 | page 22 of 28 03735-0-023 figure 25. power plane 1 03735-0-024 figure 26. power plane 2 03735-0-025 figure 27. first ground plane 03735-0-026 figure 28. second ground plane
ad12400 rev. 0 | page 23 of 28 03735-0-027 figure 29. top side copper 03735-0-028 figure 30. bottom side copper 03735-0-029 figure 31. top mask 03735-0-030 figure 32. top silkscreen 03735-0-031 figure 33. bottom silkscreen 03735-0-032 figure 34. evaluation adapter boardtop silkscreen
ad12400 rev. 0 | page 24 of 28 03735-0-033 figure 35. evaluation adapter boardanalog and digital layers 03735-0-034 figure 36. evaluation adapter boardbottom silkscreen
ad12400 rev. 0 | page 25 of 28 layout guidelines the ad12400 requires a different approach to traditional high speed analog-to-digital converter system layouts. while the ad12400s internal pcb isolates digital and analog grounds, these planes are tied together through the products aluminum case structure. therefore, the decision of isolating the analog and digital grounds on the system pcb has additional factors to consider. for example, if the ad12400 will be attached with conductive thermal interface material to the system pcb, there will be essentially no benefit to keeping the analog and digital ground planes separate. if either no thermal interface material or nonconductive interface material is used, system architects will have to consider the ground loop that will be created if analog and digital planes are tied together directly under the ad12400. this emi based decision will have to be considered on a case-by-case basis and will be largely dependent on the other sources of emi in the system. one critical consideration is that a 12-bit performance requirement (C74 dbc) will require keeping conducted emi currents (referenced to the input of the ad12400) below 4.5 a. all of the characterization and testing of the ad12400 was performed using a system that isolated these ground planes. if thermal interface material is used in the final system design, the following layout factors will need to be considered: open solder mask on the area that contacts the interface material and the thickness of the ground plane. while this should be analyzed in each specific system design, the use of solder mask may negate any advantage achieved by using the thermal interface material, and its use should be carefully considered. the ground plane thickness will not have a major impact on the thermal performance, but if design margin is slight, additional thickness can yield incremental improvements. pcb interface figure 37 provides the mounting hole footprint for assembling the ad12400 to the second-level assembly. the diagram is referenced to the center of the mating qte connector. refer to the qte/qse series connector documentation at www.samtec.com for the smt footprint of the mating connector. the top view of the second-level assembly footprint provides a diagram of the second-level assembly locating tab locations for mating the samtec qte-060-01- l-a-k-tr terminal strip on the ad12400bws to a qse-060-01-l-a-k-tr socket on the second-level assembly. the diagram is referenced to the center of the qte terminal strip on the ad12400bws and the mounting holds for the screws, which will hold the ad12400bws to the second-level assembly board. the relationship of these locating tabs is based on information provided by samtec (connector supplier) and should be verified with samtec by the customer. mating and unmating forcesthe knifing or peeling action of applying force to one end or one sidemust be avoided to prevent damage to the connector and guidepost.
ad12400 rev. 0 | page 26 of 28 03735-0-035 1.184 [30.0673] 1.184 [30.0673] r.0470[r1.19] 6 1.025 [26.0164] 2 0.105 [2.6670] 2 0.396 [10.0456] 2 2.159 [54.8258] 2 1.025 [26.0164] 2 .000 [.0000] 0.000 [.0000] 0, 0 datum = center of connector figure 37. top view of interface pcb assembly
ad12400 rev. 0 | page 27 of 28 outline dimensions top view side view 3.190 typ pin 1 ain enc enc 2.890 max board 2.328 typ 0.856 typ 0.256 typ 0.267 typ samtec connector qte-060-01-l-d-a-k-tr bottom view 1.773 1.753 2.060 2.040 0.270 2 0.505 typ 2 0.700 max 0.175 typ 0.200 typ 2-56 studs 4 0.600 max johnson sma-50 ohm connect no. 142-0711-821 2.590 max 2.060 2.040 figure 38. outline dimensions dimensions shown in inches tolerances: 0.xx = 10 mils 0.xxx = 5 mils ordering guide model temperature range package description ad12400kws 0c to 60c (case) 2.9" 2.6" 0.6" ad12400jws 0c to 60c (case) 2.9" 2.6" 0.6" ad12400/kit 25c evaluation kit
ad12400 rev. 0 | page 28 of 28 ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03735-0-11/03(0)

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